As demand for higher device densities on silicon wafers has increased, the size of individual devices has had to shrink. In particular, in the construction of Metal Oxide Semiconductor Field Effect Transistor (MOSFET) gates, the channel lengths have been reduced. As channel lengths have decreased, in particular to lengths less than about 1.5.mu.m, the influence of hot carrier effects has become more and more pronounced. Hot carrier effects in FETs are generally caused by damage to the silicon substrate in the immediate vicinity of the gate. This damage is caused by the conventional processing steps in gate construction and by source and drain doping.
Also, the formation of reliable metal gates in CMOS VLSI structures has heretofore been difficult. The low selectivity between metal and silicon dioxide ("oxide") in a typical etch process make is difficult to control the size and shape of metal pattern gates. In a typical etch step, the silicon substrate is often damaged. This damage results in poor hot carrier effect performance and also creates other problems that result in low wafer yield.
Discussion of the Prior Art
Various strategies for improving device performance and chip yield have been suggested. For example, U.S. Pat. No. 5,434,093 for INVERTED SPACER TRANSISTOR; issued Jul. 18, 1995 to Robert S. Chau, et al., teaches a method for forming narrow length transistors by forming a trench in a first layer over a semiconductor. Spacers and gate dielectric are formed and then the trench is filled with gate electrode material which is chemically-mechanically polished back to isolate the gate material within the trench. The first layer is then removed leaving the gate dielectric, gate electrode and spacers.
In U.S. Pat. No. 5,489,543 for METHOD OF FORMING A MOS DEVICE HAVING A LOCALIZED ANTI-PUNCHTHROUGH REGION; issued Feb. 6, 1996 to Gary Hong discloses a method for forming a MOS device having a localized anti-punchthrough region which is adjacent to but not in contact with source/drain regions of the MOS device. A trench is formed by depositing a conducting layer on an oxide layer located on a channel region of the MOS device. The trench is used as a self-alignment mask for subsequent implantation processes to form the localized anti-punchthrough region.
In U.S. Pat. No. 5,538,913 for PROCESS FOR FABRICATING MOS TRANSISTORS HAVING FULL-OVERLAP LIGHTLY-DOPED DRAIN STRUCTURES; issued Jul. 23, 1996 to Gary Hong, another method for constructing drain regions is taught. An oxide layer on a semiconductor substrate defines an active region foe the MOS device. The oxide layer serves as a shielding mask for implantation of a lightly-doped region. A shielding layer is next formed with an opening over the substrate, the opening having two side walls that define a channel region. Gate insulation is formed at the opening and then spacers are added at the side walls. The channel region is implanted using the spacers as a shielding mask. A conducting layer is formed over the surface of the gate thereby forming the MOS device. The shielding layer is removed and the remaining gate and field oxide layers are used as masks for additional implantation forming a heavily-doped region where the lightly-doped region completely overlaps the gate and extends into the drain and source regions of the MOS device.
Finally, U.S. Pat. No. 5,670,401 for METHOD FOR FABRICATING A DEEP SUBMICRON MOSFET DEVICE USING AN IN-SITU POLYMER SPACER TO DECREASE DEVICE CHANNEL LENGTH; issued Sep. 23, 1997 to Horng-Huei Tseng teaches a fabrication technique wherein a polymeric spacer is formed in a photo resist layer. The polymeric spacer reduces the opening in the photo resist to a width narrower than that obtainable through conventional lithographic/etch techniques thereby allowing the formation of a narrow gate structure overlaying a local threshold adjust region implanted in the silicon substrate. In contradistinction, the inventive method requires no polymer spacer to control gate width but relies on a unique sequence of processing steps to form a reliable metal gate while preserving a pad oxide layer under a normal silicon oxide spacer.
No combination of these prior art references are seen to teach or suggest the inventive process for forming the recessed, metal-gate CMOS devices of the instant invention.